Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
| Author | : | |
| Rating | : | 4.85 (920 Votes) |
| Asin | : | 904817922X |
| Format Type | : | paperback |
| Number of Pages | : | 280 Pages |
| Publish Date | : | 2013-08-14 |
| Language | : | English |
DESCRIPTION:
Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. Included are examples of practical circuits (PCI, AMBA, Wishbone-PIC, CPU Pipeline) and their assertion checker synthesis.. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage of the modern assertion languages, with a focus on o
Dr. Klaus Winkelmann said Solid standard work for PSL/SVA implementors. Based on Boulé's PhD thesis, the book gives an excellent in-depth view of concepts and algorithms for checking PSL and SVA assertions. The treatment of automata for SEREs and properties, including determinisation and hardware implementation, is clear and comprehensive. It applies to formal as well as simulative checkers. Unfortunately, a few important topics are missing, namely cons
This book presents an "under-the-hood" view of generating assertion checkers. It gives a unique and consistent perspective on employing assertions in such areas as specification, verification, debugging, on-line monitoring and design quality improvement.